With the continued miniaturization of integrated circuit (IC) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies. All of these processes cause the related CMOS IC products to become more susceptible to damage due to ESD events. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits on the IC from ESD damage. ESD protection is especially challenging for RF ICs in view of the reduced gate oxide thicknesses and lowered breakdown voltages in the devices of the RF ICs.
FIG. 1 illustrates one example of a conventional ESD protection device 100 including a gate grounded NMOS (GGNMOS) transistor 102 having its source also coupled to ground and its drain coupled to a node 108 between a pad 106 and a resistor 104. FIG. 2 illustrates a distributed ESD protection arrangement 200 including a plurality of GGNMOS transistors 202-1:202-4 having their sources coupled to ground and their drains coupled to a respective PMOS transistor 204-1:204-4 through an n-type well having a resistance R. Each of the PMOS transistors has its gate and source coupled to a positive supply voltage node VDD. However, such an arrangement increases the device size and consequently contributes to a large parasitic capacitance.
FIG. 3A is a plan view of another example of an ESD protection arrangement 300, and FIG. 3B is a cross-sectional view of the ESD protection device 300, which is a single finger configuration shallow trench isolation (STI) diode. As shown in FIGS. 3A and 3B, the STI diode includes an n-type well (n-well) 304 formed over a p-type substrate 302. Two N+ regions 306-1, 306-2 are formed over n-well 304 and are laterally spaced from one another. A P+ region 308 is disposed between the N+ regions 306-1, 306-2. STI regions 310-1:310-4 are disposed adjacent to each of the N+ and P+ regions 306-1, 306-2, 308 over n-well 304. While the STI diode 300 provides low capacitance and a small area, its parasitic capacitance and resistance impact RF input matching, and its performance degrades for high frequency RF applications.
Accordingly, an improved ESD protection scheme is desirable.